1. Field of the Invention
This invention relates generally to systems and methods involving digital to analog converters, and specifically to systems and methods for operating digital and analog converters more efficiently.
2. Description of Background
Some digital to analog converters (DACs) include a network of series resistors that is disposed between a first reference (VREF1) and a second reference (VREF2). A prior art example of a DAC is shown in FIG. 1. Each of the resistors in the network is similar to the other resistors in the network. The voltage (VREF1-VREF2) is divided such that an equal voltage drop occurs across each resistor in the network. A series of analog multiplexor (MUX) devices is disposed between each of the nodes between the resistors in the network and an output node. Activation of a MUX device allows propagation of a selected voltage node from the resistor network to the DAC output (DAC Out). The DAC Out has some capacitive loading and may drive a high-swing operational amplifier to drive off-chip circuits or remain unbuffered to drive an on-chip ADC reference input.
The resistor network of FIG. 1 grows with an increasing number of bits into the incoming digital signature or address. A 2-bit resolution DAC uses 4 resistors; a 4-bit resolution DAC uses 16 resistors; an 8-bit resolution DAC uses 256 resistors and a 10-bit resolution DAC uses 1024 resistors in series. As the number of resistors grows, the total resistance of the network grows, increasing the RC time constant for charging and discharging output DAC Out as the address changes. As a result, performance of the resistor DAC is limited. With growth in resistor count, resistor tracking becomes a concern across the larger array, impacting DAC integral non linearity (INL) and differential non linearity (DNL). The size of the unit resistor in the network can be reduced, but cannot be scaled at the same rate that the number of resistors is increased. Further, decreasing the unit resistance may contribute to increased DAC INL and DNL if resistor length is decreased to decrease total resistance and will increase area if resistor width is increased to decrease total resistance of the DAC.